Scan chain is a technique used in design for testing. The objective is to make testing easier by providing a simple way to set and observe every flip-flop in an IC.The basic structure of scan include the following set of signals in order to control and observe the scan mechanism.

1. Scan_in and scan_out define the input and output of a scan chain. In a full scan mode usually each input drives only one chain and scan out observe one as well.
2. A scan enable pin is a special signal that is added to a design. When this signal is asserted, every flip-flop in the design is connected into a long shift register.
3. Clock signal which is used for controlling all the FFs in the chain during shift phase and the capture phase. An arbitrary pattern can be entered into the chain of flip-flops, and the state of every flip-flop can be read out.

In a full scan design, automatic test pattern generation (ATPG) is particularly simple. No sequential pattern generation is required - combinatorial tests, which are much easier to generate, will suffice. If you have a combinatorial test, it can be easily applied.

• Assert scan mode, and set up the desired inputs.
• De-assert scan mode, and apply one clock. Now the results of the test are captured in the target flip-flops.
• Re-assert scan mode, and see if the combinatorial test passed.

In a chip that does not have a full scan design -- i.e., the chip has sequential circuits, such as memory elements that are not part of the scan chain, sequential pattern generation is required. Test pattern generation for sequential circuits searches for a sequence of vectors to detect a particular fault through the space of all possible vector sequences.

Even a simple stuck-at fault requires a sequence of vectors for detection in a sequential circuit. Also, due to the presence of memory elements, the controllability and observability of the internal signals in a sequential circuit are in general much more difficult than those in a combinational logic circuit. These factors make the complexity of sequential ATPG much higher than that of combinational ATPG.

There are many variants:

• Partial scan: Only some of the flip-flops are connected into chains.
• Multiple scan chains: Two or more scan chains are built in parallel, to reduce the time to load and observe.
• Test compression: the input to the scan chain is provided by on-board logic.

• Design for testing
• Automatic test pattern generation
• Electronic design automation
• Integrated circuit design
• Serial Peripheral Interface Bus
• Iddq testing

• An example of a scan chain for stuck-at faults